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FMS72509
Phase Locked Loop Clock Driver
Features
* * * * * * * * * * PC-133 Spread Spectrum Compliant Frequency Range of 25 to 140 MHz VDD Range of 3.0 to 3.6 Volts Up to 11 outputs Less than 100 pS of Output to Output Skew Less than 90 pS of Cycle to Cycle Jitter Output Enable pin Integrated Damping Resistor Commercial Temperature Range Available in 24 pin TSSOP
Description
FMS72509 is a zero delay clock buffer designed for high fan out applications. It contains 10 outputs. It provides precise phase and frequency alignment between incoming clock and the output clocks. This makes it ideal for high speed application in the range of 25 to 140 MHz. The Phase Locked Loop is capable of tracking incoming clock modulation of up to 1% of the clock period. With the exception of FBOUT, the output Enable (OE) pin, when pulled low, will force the outputs to logic low.
Block Diagram
OE1
FB O U T Q0 Q1 Q2 Q3 FBIN PLL CLKIN Control Logic Q4 Q5 Q6 Q7 Q8 Q9 OE2
REV. 1.0 8/11/00
PRODUCT SPECIFICATION
FMS72509
Pin Assignments
24 TSSO P AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD O E1 FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 FMS72509 24 23 22 21 20 19 18 17 16 15 14 13 CL KI N AVDD VDD Q8 Q7 GND GND Q6 Q5 VDD OE2 FB I N
Pin Description
Pin Name GND AGND VDD AVDD Q(0:4) OE1 FBOUT FBIN OE2 VDD Q(5:8) CLKIN Pin # 6, 7, 18, 19 1 2, 10, 15, 22 23 3, 4, 5, 8, 9 11 12 13 14 15 16,17, 20, 21 24 Pin Type PWR PWR PWR PWR OUT IN OUT IN IN PWR OUT IN Pin Function Description Ground Connection: Connect all ground pins to the common system ground plane. Analog Ground Connection: Connect to common system ground plane. Power Connection: Power supply for all the outputs. Power Connection: Power supply for the PLL. In addition, it can be used to bypass the PLL. Clock outputs: Clock outputs 0:4 are buffer clocks of input. Outputs Enable 1: When low, outputs, with the exception of FBOUT, Q0 to Q4 are to logic low. Normal operation when asserted high. Feedback Clock Output: Dedicated pin for FB pin. It is not effected by OE pin. Feedback Clock Input: PLL feedback input. The user connects it to FBOUT. Outputs Enable 2: When low, outputs 5:8 are logic low. Normal operation when asserted high. This function is only for FMS72509. Power Connection: Power supply for PLL. Connect to 3.3V. Clock outputs: Outputs are buffer clocks of input. Input Clock: Input clock to the PLL.
Functionality Table
AVDD L L L H H H OE1 L L H L L H OE2 L H L L H H PLL BYPASS BYPASS BYPASS Enabled Enabled Enabled Q(0:4) L L X(1) L L Note 2 Q(5:8) L X(1) L L Note 2 Note 2 FBOUT X(1) X(1) X(1) Note 2 Note 2 Note 2
NOTES: 1. Depending on the state of the CLKIN, it will be High or Low. 2. Lock in phase with CLKIN.
2
REV. 1.0 8/11/00
FMS72509
PRODUCT SPECIFICATION
Absolute Maximum Rating
Symbol VDD, VIN TSTG TB TA Storage Temperature Ambient Temperature Operating Temperature Parameter Voltage on any pin with respect to ground Ratings -0.5 to 7.0 -65 to 150 -55 to 125 0 to 70 Units V C C C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
TA = 0 to 70C; Supply Voltage 3.3 V 0.3V (unless otherwise stated) Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current High Output Voltage Low Output Voltage Input Capacitance Supply Current Clock Stabilization
(1) (1)
Symbol VIL VIH IIL IIH VOH VOL CIN IDD TSTAB VIN = 0 VIN = VDD IOH = -6mA IOL = 15mA
Conditions
Min. GND - 0.3 2.0 -10 -10 2.4 2.5
Typ.
Max. 0.8 VDD + 0.3 10 10
Units V V A A V V pF mA mA mS
3.1 0.5 200 230 0.8 6.0 290 320 1
Frequency = 10MHz Frequency = 100 MHz; CL = 12pF Frequency = 133 MHz; CL = 12pF From VDD = 3.3 V to 1% Target
NOTE: 1. Guaranteed by design, not subject to 100% production testing.
AC Electrical Characteristics
TA = 0 to 70C; Supply Voltage VDD = 3.3V 0.3V, CL = 12 pF (unless otherwise stated) Parameter Clock Input Duty Cycle Rise Time(1) Fall Time
(1) (1) (1) (1) (1)
Symbol DT_IN FIN TR TF DT TJIT TSK_SSC TSK1 TSK2
Conditions AVDD = 3.3V 0.4 to 2.0V 2.0 to 0.4V VTH = 1.25V VTH = 1.25V; 100 & 133MHz VTH = VDD/2 VTH = VDD/2 CLFB = 4 pF;100 & 133MHz
Min. 40 25 - - 40 -120 -200 -120 -100
Typ.
Max. 60 140
Units % MHz nS nS % pS pS pS pS
Input Frequency Range
1.0 1.0
2.0 2.0 60 120 200 120 100
Duty Cycle
Jitter (Cycle-Cycle)
Spread Spectrum Induced Skew Output to Output Skew(1) Input to Output Delay
(1,2)
NOTE: 1. Guaranteed by design, not subject to 100% production testing. 2. Feedback trace length of 0.7".
REV. 1.0 8/11/00
3
PRODUCT SPECIFICATION
FMS72509
Parameter Measurement Information
Duty Cycle Timing (DT)
t1 t2 DT = 1.5V 1.5V 1.5V
t2 t1
x 100
Rise/Fall Time (TR/TF)
2.0V 0.4V OUTPUT 2.0V 0.4V 0V 3.3V
TR
TF
Output to Output Skew (TSK1)
1.5V Q0
1.5V Any Output TSK1
Input to Output Delay (TSK2)
1.5V CLKIN 1.5V FBIN TSK2
4
REV. 1.0 8/11/00
FMS72509
PRODUCT SPECIFICATION
Application Diagram
CLKIN IN Q0
PLL QN FBIN C FBOUT
Note: Feedback capacitor value 'C' is to be determined based on the phase characteristics of the PLL.
REV. 1.0 8/11/00
5
PRODUCT SPECIFICATION
FMS72509
Mechanical Dimensions
24-Lead TSSOP Package
Symbol A A1 B C D E e H L N ccc Inches Min. -- .002 .007 .004 .308 Max. .047 .006 .012 .008 .316 Millimeters Min. -- 0.05 0.19 0.09 7.70 Max. 1.20 0.15 0.30 0.20 7.90 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. Symbol "N" is the maximum number of terminals. 2 2
.172 .180 .026 BSC .256 BSC .018 .030 24 0 -- 8 .004
4.30 4.50 0.65 BSC 6.40 BSC 0.45 0.75 24 0 -- 8 0.10
3 5
D
E
H
A B e
A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
C
6
REV. 1.0 8/11/00
PRODUCT SPECIFICATION
FMS72509
Ordering Information
Product Number FMS72509MTC Tape & Reel FMS72509MTCT Package TSSOP-24
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
8/11/00 0.0m 002 Stock#DS300072509 (c) 2000 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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